Paper #2

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

Md. Shahriar Khan Hemel, Mamun Bin Ibne Reaz, Sawal Hamid Bin Md Ali, Mohammad Arif Sobhan Bhuiyan and Mahdi H. Miraz

Abstract: The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps.

Keywords: Cadence virtuoso; Digital circuit; Optimisation; Phase-locked loop (PLL); Phase frequency detector (PFD); 90 nm CMOS.